Design of analog front-ends for the RD53 demonstrator chip

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment

Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.Comment: 45 pages, 30 figures, submitted to JINS

Planar pixel sensors for the ATLAS upgrade: beam tests results

Results of beam tests with planar silicon pixel sensors aimed towards the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include spatial resolution, charge collection performance and charge sharing between neighbouring cells as a function of track incidence angle for different bulk materials. Measurements of n-in-n pixel sensors are presented as a function of fluence for different irradiations. Furthermore p-type silicon sensors from several vendors with slightly differing layouts were tested. All tested sensors were connected by bump-bonding to the ATLAS Pixel read-out chip. We show that both n-type and p-type tested planar sensors are able to collect significant charge even after integrated fluences expected at HL-LHC

Planar pixel sensors for the ATLAS upgrade: beam tests results

Results of beam tests with planar silicon pixel sensors aimed towards the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include spatial resolution, charge collection performance and charge sharing between neighbouring cells as a function of track incidence angle for different bulk materials. Measurements of n-in-n pixel sensors are presented as a function of fluence for different irradiations. Furthermore p-type silicon sensors from several vendors with slightly differing layouts were tested. All tested sensors were connected by bump-bonding to the ATLAS Pixel read-out chip. We show that both n-type and p-type tested planar sensors are able to collect significant charge even after integrated fluences expected at HL-LHC.Comment: 28 pages, 27 figures, published on Journal of Instrumentation (JINST

Planar pixel sensors for the ATLAS upgrade: beam tests results

Results of beam tests with planar silicon pixel sensors aimed towards the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include spatial resolution, charge collection performance and charge sharing between neighbouring cells as a function of track incidence angle for different bulk materials. Measurements of n-in-n pixel sensors are presented as a function of fluence for different irradiations. Furthermore p-type silicon sensors from several vendors with slightly differing layouts were tested. All tested sensors were connected by bump-bonding to the ATLAS Pixel read-out chip. We show that both n-type and p-type tested planar sensors are able to collect significant charge even after integrated fluences expected at HL-LHC.Comment: 28 pages, 27 figures, published on Journal of Instrumentation (JINST

Planar pixel sensors for the ATLAS upgrade: beam tests results

Results of beam tests with planar silicon pixel sensors aimed towards the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include spatial resolution, charge collection performance and charge sharing between neighbouring cells as a function of track incidence angle for different bulk materials. Measurements of n-in-n pixel sensors are presented as a function of fluence for different irradiations. Furthermore p-type silicon sensors from several vendors with slightly differing layouts were tested. All tested sensors were connected by bump-bonding to the ATLAS Pixel read-out chip. We show that both n-type and p-type tested planar sensors are able to collect significant charge even after integrated fluences expected at HL-LHC.Comment: 28 pages, 27 figures, published on Journal of Instrumentation (JINST

Test results and prospects for RD53A, a large scale 65 nm CMOS chip for pixel readout at the HL-LHC

The CERN RD53 collaboration was founded to tackle the extraordinary challenges associated with the design of pixel readout chips for the innermost layers of particle trackers at future high energy physics experiments. Around 20 institutions are involved in the collaboration, which has the support of both ATLAS and CMS experiments. The goals of the collaboration include the comprehensive understanding of radiation effects in the 65 nm technology, the development of tools and methodology to efficiently design large complex mixed signal chips and, ultimately, the development of a full size readout chip featuring a 400 × 400 pixel array with 50μm pitch. In August 2017, the collaboration submitted the large scale chip RD53A, integrating a matrix of 400 × 192 pixels and embodying three different analog front-end designs. This work discusses the characteristic of the RD53A chip, with some emphasis on the analog processors, and presents the first test results on the pixel array

Mejorar el desarrollo de la comprensión lectora de los estudiantes de la I.E. Juan Pablo II

Trabajo academicoLa naturaleza del proyecto de innovación educativa es pedagógica, porque la superación del problema educativo detectado conlleva la imperiosa necesidad de, implementar talleres de estrategias metodológicas a cargo de un experto, para que los docentes puedan aplicarlas en las sesiones de aprendizaje , de modo que los niños puedan adquirir esta fundamental habilidad, y es también de formación docente, porque hoy por hoy un paradigma actual es la disposición positiva que debe tener todo docente para seguir aprendiendo y reaprendiendo de modo continuo y permanente, donde los procesos de asimilación, reflexión e interiorización sean frecuentes y nos permitan desarrollar actitudes de crítica y toma de decisiones en un ambiente de aprendizaje significativo. Ontoria (1945) Las dimensiones de la gestión, que se abordarán con el proyecto son: la dimensión Institucional que deberá incluirse como política institucional la mejora gradual y permanente de la comprensión lectora de los estudiantes de la I.E. a mediano plazo, involucrando a toda la Comunidad educativa en el reto, de igual modo la dimensión Pedagógica acogerá la ejecución del proyecto ya que una buena planificación es la base de un aprendizaje significativo para nuestros alumnos, por lo que es imprescindible preparar con anticipación nuestras sesiones tomando en cuenta las necesidades, intereses y potencialidades de los alumno

Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC

International audienceThe RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, in order to face the unprecedented design requirements of the pixel 2 phase upgrades of the CMS and ATLAS experiments at CERN. This prototype chip is designed to demonstrate that a set of challenging specifications can be met, such as: high granularity (small pixels of 50×50 or 25× 100 µm2) and large pixel chip size (~2x2 cm2), high hit rate (3 GHz/cm2), high readout speed, very high radiation levels (500 Mrad - 1 Grad) and operation with serial powering. Furthermore, coping with the long latency of the trigger signal (~12.5 µs), used to select only events of interest in order to achieve sustainable output data rates, requires increased buffering resources in the limited pixel area. The RD53A chip has been fabricated in an engineer run. It integrates a matrix of 400×192 pixels and features various design variations in the analog and digital pixel matrix for testing purposes. This paper presents an overview of the chip architecture and of the methodologies used for efficient design of large complex mixed signal chips for harsh radiation environments. Experimental results obtained from the characterization of the RD53A chip are reported to demonstrate that design objectives have been achieved. Moreover, design improvements and new features being developed in the RD53B framework for final ATLAS and CMS production chips are discusse